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Details of 13.1 Software and IP Changes
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Device View Enhancements
PlanAhead Release 13 contains the following enhancements.
Device Resource Details
The device view in PlanAhead has been enhanced to provide more detail for device
resources such as pins on slices and BEL-level pins for Virtex?-6 and Virtex-7 devices,
and the Timing Path provides annotation on pins upon full placement.
Multiple Instance Drag and Drop
PlanAhead now allows moving multiple instances in the device view at the same time.
This allows users to move instances that are already placed in a group and all location
constraints are translated together.
Schematic View Enhancements
PlanAhead supports tracing logic between two selected objects in the schematic view.
Any two objects may be selected, and PlanAhead will trace and draw any intermediate
logic connections between them within a schematic.
XPA Integration
PlanAhead Release 13 has added the ability to launch Xilinx Power Analyzer (XPA) to
analyze power on implemented designs. To launch XPA click on the XPower Analyzer
icon after opening an implemented design.
RTL Design Additions and Modifications
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Text Editor Options
PlanAhead release 13 allows for customization of fonts for comments, and keywords,
supports integration of third party text editors, and allows for easier use of Xilinx
Language Templates. See PlanAhead User Guide (UG632), Chapter 5, RTL Design.
IP Catalog
The PlanAhead release 13 enhancements in the IP Catalog are:
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The CORE Generator? IP catalog now supports migration of older superseded
cores to the currently supported version.
PlanAhead now supports canceling IP generation tasks that block other
operations in the GUI.
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Source File Exploration
PlanAhead can determine the top-module in an RTL design automatically, or give you
the ability to define it manually.
You can automatically or manually reorder source files for compilation and synthesis,
and automatically or manually enable or disable RTL source files as required by the
top-level module.
Power Estimation Enhancements
PlanAhead release 13 has Power Estimation available on Virtex-5, Virtex-6, and
Spartan-6 device families.
Partitions Control
PlanAhead release 13 provides control of partitions at the RTL level in synthesis with
XST.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.1)
www.xilinx.com
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相关PDF资料
EF-EDK-FL SOFTWARE EDK EMBED FLOAT
EF-ISE-DSP-FL SOFTWARE ISE DSP EDITION
EF-ISE-SYSTEM-FL ISE DESIGN SYST FLOATING LICENSE
EF-VIVADO-HLS-FL VIVADO HLS, FLOATING LICENSE
EFM32-GXXX-PTB BOARD PROTOTYPING FOR EFM32
EFS315 FUSE INDUST 315A 415V BS IEC
EHBNCSCB CONN EH BNC T/H SOLDER CUP BLK
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EFE01A-F 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM)
EFE01A-S 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM)
EFE01A-SE 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM)
EFE01B 制造商:CRYDOM 制造商全称:Crydom Inc., 功能描述:Power Modules